`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/12/10 21:27:37
// Design Name:
// Module Name: Computer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Computer(
    input clk,
    input rst,

    // uart
    input uart_rx_pin,
    output uart_tx_pin,

    // LED
    output over,
    output succ
  );

  localparam  SYS_FRENCY =50_000_000;//系统频率50M
  localparam  BAUD_FRENCY =115200;//波特率

  logic [15:0]inM;
  logic [15:0]instruction;
  logic [15:0]outM;
  logic writeM;
  logic [15:0]addressM;
  logic [15:0] pc;

  // uart
  logic [15:0] uart_out;
  logic load_uart;

  CPU cpu(
        // input
        .clk(clk),
        .rst(rst),
        .inM(inM),
        .instruction(instruction),

        // output
        .outM(outM),
        .writeM(writeM),
        .addressM(addressM),
        .pc(pc)
      );

  ROM32K rom(
           // input
           .clk(clk),
           .rst(rst),
           .address(pc),
           // output
           .out(instruction));

  Memory mem(
           // input
           .clk(clk),
           .rst(rst),
           .in(outM),
           .load(writeM),
           .address(addressM),
           // uart
           .uart_in (uart_out),
           .load_uart (load_uart),
           // output
           .out(inM) // 送给 CPU
         );

  uart
    #(.SYS_FRENCY(SYS_FRENCY),
      .BAUD_FRENCY(BAUD_FRENCY))
    uart (
      .clk         (clk)         ,
      .rst         (rst)         ,
      .in          (outM)        ,
      .load        (load_uart)    ,
      .address     (addressM)    ,
      .uart_rx_pin (uart_rx_pin) ,
      .uart_tx_pin (uart_tx_pin) ,
      .out         (uart_out)
    );

  assign over = 1'b1;
  assign succ = 1'b1;
endmodule
